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| 19-1357; Rev 1; 7/98 KIT ATION EVALU BLE AVAILA High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP General Description ____________________________Features o 96% Efficiency o Small, 16-Pin QSOP Package (half the size of a 16-pin narrow SO) o Pin-Compatible with MAX797 (MAX1653/MAX1655) o Output Voltage Down to 1V (MAX1655) o 4.5V to 30V Input Range o 99% Duty Cycle for Lower Dropout o 170A Quiescent Supply Current o 3A Logic-Controlled Shutdown o Dual, N-Channel, Synchronous-Rectified Control o Fixed 150kHz/300kHz PWM Switching, or Synchronized from 190kHz to 340kHz o Programmable Soft Start o Low-Cost Secondary Outputs (MAX1652/MAX1654) MAX1652-MAX1655 The MAX1652-MAX1655 are high-efficiency, pulsewidth-modulated (PWM), step-down DC-DC controllers in small QSOP packages. The MAX1653/MAX1655 also come in 16-pin narrow SO packages that are pincompatible upgrades to the popular MAX797. Improvements include higher duty-cycle operation for better dropout, lower quiescent supply currents for better light-load efficiency, and an output voltage down to 1V (MAX1655). The MAX1652-MAX1655 achieve up to 96% efficiency and deliver up to 10A using a unique Idle ModeTM synchronous-rectified PWM control scheme. These devices automatically switch between PWM operation at heavy loads and pulse-frequency-modulated (PFM) operation at light loads to optimize efficiency over the entire output current range. The MAX1653/MAX1655 also feature logic-controlled, forced PWM operation for noise-sensitive applications. All devices operate with a selectable 150kHz/300kHz switching frequency, which can also be synchronized to an external clock signal. Both external power switches are inexpensive N-channel MOSFETs, which provide low resistance while saving space and reducing cost. The MAX1652 and MAX1654 have an additional feedback pin that permits regulation of a low-cost second output tapped from a transformer winding. The MAX1652 provides an additional positive output. The MAX1654 provides an additional negative output. The MAX1652-MAX1655 have a 4.5V to 30V input voltage range. The MAX1652/MAX1653/MAX1654's output range is 2.5V to 5.5V while the MAX1655's output range extends down to 1V. An evaluation kit (MAX1653EVKIT) is available to speed designs. Ordering Information PART MAX1652EEE MAX1653ESE MAX1653EEE MAX1654EEE MAX1655ESE MAX1655EEE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 16 QSOP 16 Narrow SO 16 QSOP 16 QSOP 16 Narrow SO 16 QSOP Applications Notebook Computers PDAs Cellular Phones Hand-Held Computers Handy-Terminals Mobile Communicators Distributed Power MAX1654 2.5 MAX1653 2.5 MAX1652 2.5 PART FEEDBACK VOLTAGE (V) Selection Guide SPECIAL FEATURE COMPATIBILITY Regulates positive Same pin order secondary voltage as MAX796, but (such as +12V) smaller package Logic-controlled, Pin-compatible low-noise mode with MAX797 Regulates negative Same pin order secondary voltage as MAX799, but (such as -5V) smaller package Low output voltages (1V to 5.5V); logic-controlled, low-noise mode Pin compatible with MAX797 (except for feedback voltage) Pin Configurations appear at end of data sheet. Idle Mode is a trademark of Maxim Integrated Products. MAX1655 1 ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 ABSOLUTE MAXIMUM RATINGS V+ to GND ..............................................................-0.3V to +36V GND to PGND .......................................................-0.3V to +0.3V VL to GND ................................................................-0.3V to +6V BST to GND ............................................................-0.3V to +36V DH to LX .....................................................-0.3V to (BST + 0.3V) LX to BST..................................................................-6V to +0.3V SHDN to GND...............................................-0.3V to (V+ + 0.3V) SYNC, SS, REF, SECFB, SKIP, FB to GND...-0.3V to (VL + 0.3V) DL to PGND ..................................................-0.3V to (VL + 0.3V) CSH, CSL to GND ....................................................-0.3V to +6V VL Short Circuit to GND..............................................Momentary REF Short Circuit to GND ...........................................Continuous VL Output Current ...............................................+50mA to -1mA REF Output Current...............................................+5mA to -1mA Continuous Power Dissipation (TA = +70C) SO (derate 8.70mW/C above +70C) .......................696mW QSOP (derate 8.3mW/C above +70C) ....................667mW Operating Temperature Range MAX165_E_E ..................................................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = +15V, GND = PGND = 0V, SYNC = REF, IVL = IREF = 0A, TA = 0C to +85C, unless otherwise noted.) PARAMETER 3.3V AND 5V STEP-DOWN CONTROLLERS Input Supply Range 5V Output Voltage (CSL) 3.3V Output Voltage (CSL) Nominal Adjustable Output Voltage Range 0 < (CSH - CSL) < 80mV, FB = VL, 6V < V+ < 30V, includes line and load regulation 0 < (CSH - CSL) < 80mV, FB = 0V, 4.5V < V+ < 30V, includes line and load regulation MAX1655 External resistor divider MAX1652/MAX1653/ MAX1654 MAX1655 Feedback Voltage CSH - CSL = 0V, CSL = FB, SKIP = 0V, 4.5V < V+ < 30V 0 < (CSH - CSL) < 80mV 25mV < (CSH - CSL) < 80mV 6V < V+ < 30V CSH - CSL, positive CSH - CSL, negative VSS = 0V VSS = 4V Falling edge, rising edge, hysteresis = 22mV (MAX1652) Rising edge, falling edge, hysteresis = 22mV (MAX1654) SHDN = 2V, 0 < IVL < 25mA, 5.5V < V+ < 30V Rising edge, falling edge hysteresis = 50mV Rising edge, falling edge hysteresis = 60mV 80 -50 2.5 2.0 2.45 -0.05 4.7 3.8 4.2 2.50 0 5.0 3.9 4.5 2.55 0.05 5.3 4.0 4.7 MAX1652/MAX1653/ MAX1654 4.5 4.85 3.20 1 2.5 0.97 2.43 1.00 2.50 2 1.2 0.03 100 -100 4.0 0.06 120 -160 6.5 5.06 3.34 30 5.25 3.46 5.5 5.5 1.03 2.57 V V V V V CONDITIONS MIN TYP MAX UNITS Load Regulation Line Regulation Current-Limit Voltage SS Source Current SS Fault Sink Current FLYBACK/PWM CONTROLLER SECFB Regulation Setpoint % %/V mV A mA V INTERNAL REGULATOR AND REFERENCE VL Output Voltage VL Fault Lockout Voltage VL/CSL Switchover Voltage V V V 2 _______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP ELECTRICAL CHARACTERISTICS (continued) (V+ = +15V, GND = PGND = 0V, SYNC = REF, IVL = IREF = 0A, TA = 0C to +85C, unless otherwise noted.) PARAMETER Reference Output Voltage Reference Fault Lockout Voltage Reference Load Regulation CSL, CSH Shutdown Leakage Current V+ Shutdown Current V+ Off-State Leakage Current Dropout Power Consumption Quiescent Power Consumption Falling edge 0 < IREF < 100A SHDN = 0V, CSL = 5.5V, CSH = 5.5V, V+ = 0 or 30V, VL = 0V SHDN = 0V, V+ = 30V, CSL = 0 or 5.5V FB = CSH = CSL = 5.5V, VL switched over to CSL V+ = 4.5V, CSH = CSL = 4.0V (Note 2) CSH = CSL = 5.5V SYNC = REF SYNC = 0 or 5V 270 125 200 200 Guaranteed by design, not tested 190 SYNC = REF SYNC = 0 or 5V SYNC SHDN, SKIP SYNC SHDN, SKIP SHDN, 0 or 30V SECFB, 0 or 4V Input Current SYNC, SKIP CSH, CSL, CSH = CSL 4V FB, FB = REF DL Sink/Source Current DH Sink/Source Current DL On-Resistance DH On-Resistance DL forced to 2V DH forced to 2V, BST - LX = 4.5V High or low High or low, BST - LX = 4.5V 1 1 1.5 1.5 5 5 97 98 VL - 0.5 2.0 0.8 0.5 3.0 0.1 1.0 70 0.1 A A A 98 99 200 340 CONDITIONS No external load (Note 1) MIN 2.46 2.0 5 0.1 3 5 1 1 300 150 TYP 2.50 MAX 2.54 2.4 15 1 7 15 8 2 330 175 UNITS V V mV A A A mW mW MAX1652-MAX1655 OSCILLATOR AND INPUTS/OUTPUTS Oscillator Frequency SYNC High Pulse Width SYNC Low Pulse Width SYNC Rise/Fall Time Oscillator Sync Range Dropout-Mode Maximum Duty Cycle Input High Voltage Input Low Voltage kHz ns ns ns kHz % V V Note 1: Since the reference uses VL as its supply, V+ line-regulation error is insignificant. Note 2: At very low input voltages, quiescent supply current may increase due to excessive PNP base current in the VL linear regulator. This occurs if V+ falls below the preset VL regulation point (5V nominal). _______________________________________________________________________________________ 3 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 ELECTRICAL CHARACTERISTICS (continued) (V+ = +15V, GND = PGND = 0V, SYNC = REF, IVL = IREF = 0A, TA = -40C to +85C, unless otherwise noted.) (Note 3) PARAMETER 3.3V and 5V STEP-DOWN CONTROLLERS Input Supply Range 5V Output Voltage (CSL) 3.3V Output Voltage (CSL) 0 < (CSH - CSL) < 70mV, FB = VL, 6V < V+ < 30V, includes line and load regulation 0 < (CSH - CSL) < 70mV, FB = VL, 4.5V < V+ < 30V, includes line and load regulation MAX1655 Feedback Voltage Line Regulation Current-Limit Voltage FLYBACK/PWM CONTROLLER SECFB Regulation Setpoint Falling edge, hysteresis = 22mV (MAX1652) Falling edge, hysteresis = 22mV (MAX1654) SHDN = 2V, 0 < IVL < 25mA, 5.5V < V+ < 30V Rising edge, hysteresis = 50mV Rising edge, hysteresis = 60mV No external load (Note 1) 0 < IREF < 100A SHDN = 0V, V+ = 30V, CSL = 0 or 5.5V FB = CSH = CSL = 5.5V, VL switched over to CSL 2.40 -0.08 4.7 3.75 4.2 2.43 2.60 0.08 5.3 4.05 4.7 2.57 15 10 15 2 SYNC = REF SYNC = 0 or 5V 250 120 250 250 210 SYNC = REF SYNC = 0 or 5V High or low High or low, BST - LX = 4.5V 97 98 5 5 320 350 180 V CSH - CSL = 0V, 5V < V+ < 30V, CSL = FB, SKIP = 0V 6V < V+ < 30V CSH - CSL, positive CSH - CSL, negative 70 -40 MAX1652/MAX1653/ MAX1654 4.5 4.80 3.16 0.96 2.40 30 5.30 3.50 1.04 2.60 0.06 130 -160 V V %/V mV V V V CONDITIONS MIN TYP MAX UNITS INTERNAL REGULATOR AND REFERENCE VL Output Voltage VL Fault Lockout Voltage VL/CSL Switchover Voltage Reference Output Voltage Reference Load Regulation V+ Shutdown Current V+ Off-State Leakage Current Quiescent Power Consumption OSCILLATOR AND INPUTS/OUTPUTS Oscillator Frequency SYNC High Pulse Width SYNC Low Pulse Width Oscillator Sync Range Maximum Duty Cycle DL On-Resistance DH On-Resistance kHz ns ns kHz % V V V V mV A A mW Note 3: Specifications from 0C to -40C are guaranteed by design, not production tested. 4 _______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP Typical Operating Circuits INPUT 4.5V TO 30V MAX1652-MAX1655 V+ SHDN VL MAX1653 MAX1655 DH +3.3V OUTPUT BST SS REF LX DL PGND SYNC GND SKIP FB CSH CSL INPUT 6V TO 30V V+ SHDN SECFB FB VL +12V OUTPUT MAX1652 DH +5V OUTPUT BST LX DL SS REF GND SYNC PGND CSH CSL _______________________________________________________________________________________ 5 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 Typical Operating Circuits (continued) INPUT 6V TO 30V FROM REF V+ SECFB SHDN FB VL -5V OUTPUT MAX1654 DH BST +5V OUTPUT LX DL SS REF GND SYNC CSL PGND CSH __________________________________________Typical Operating Characteristics (Circuit of Figure 1, SKIP = GND, TA = +25C, unless otherwise noted.) EFFICIENCY vs. LOAD CURRENT (3.3V/1A CIRCUIT) MAX1652 toc01 EFFICIENCY vs. LOAD CURRENT (3.3V/2A CIRCUIT) MAX1652 toc02 EFFICIENCY vs. LOAD CURRENT (3.3V/3A CIRCUIT) V+ = 6V 90 EFFICIENCY (%) MAX1652 toc03 100 V+ = 6V 90 EFFICIENCY (%) 100 V+ = 6V 100 90 EFFICIENCY (%) 80 V+ = 28V 70 V+ = 12V 60 MAX1653 f = 300kHz 50 0.001 0.01 0.1 LOAD CURRENT (A) 1 10 80 V+ = 28V 70 V+ = 12V 60 MAX1653 f = 300kHz 50 0.001 0.01 0.1 LOAD CURRENT (A) 1 10 80 70 V+ = 12V 60 V+ = 28V MAX1653 f = 300kHz 50 0.001 0.01 0.1 LOAD CURRENT (A) 1 10 6 _______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP ____________________________________Typical Operating Characteristics (continued) (Circuit of Figure 1, SKIP = GND, TA = +25C, unless otherwise noted.) EFFICIENCY vs. LOAD CURRENT (3.3V/5A CIRCUIT) MAX1652 toc04 MAX1652-MAX1655 EFFICIENCY vs. LOAD CURRENT (5V/3A CIRCUIT) MAX1652 toc04a EFFICIENCY vs. LOAD CURRENT (1.8V/2.5A CIRCUIT) MAX1655 f = 300kHz 90 EFFICIENCY (%) V+ = 6V MAX1652 toc05 100 V+ = 6V 90 EFFICIENCY (%) 100 V+ = 6V 100 90 EFFICIENCY (%) 80 V+ = 28V 70 80 V+ = 12V 70 V+ = 28V 80 70 V+ = 24V 60 V+ = 12V 60 MAX1653 f = 300kHz 0.1 1 10 50 0.001 0.01 0.1 LOAD CURRENT (A) MAX1653 f = 300kHz 1 10 60 V+ = 12V 50 0.001 50 0.001 0.01 0.01 0.1 LOAD CURRENT (A) 1 10 LOAD CURRENT (A) IDLE-MODE SUPPLY CURRENT vs. INPUT VOLTAGE (3.3V/3A CIRCUIT) MAX1652 toc06 PWM-MODE SUPPLY CURRENT vs. INPUT VOLTAGE (3.3V/3A CIRCUIT) MAX1652 toc07 SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE SHDN = 0V 8 SUPPLY CURRENT (A) MAX1652 toc08 10 MAX1653 SKIP = 0 NO LOAD SUPPLY CURRENT (mA) 1 30 25 SUPPLY CURRENT (mA) 20 15 10 5 MAX1653 SKIP = VL f = 300kHz NO LOAD 10 6 4 0.1 2 0.01 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 0 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 0 0 5 10 15 20 25 30 INPUT VOLTAGE (V) REF LOAD-REGULATION ERROR vs. REF LOAD CURRENT MAX1652 toc010 VL LOAD-REGULATION ERROR vs. VL LOAD CURRENT MAX1652 toc011 MAX1652 MAXIMUM SECONDARY OUTPUT CURRENT vs. SUPPLY VOLTAGE MAXIMUM SECONDARY CURRENT (mA) VSEC > 12.75V, +5V OUTPUT > 4.75V, CIRCUIT OF FIGURE 9 +5V LOAD = 0A MAX1652 toc12 30 25 20 15 10 5 0 0 50 100 150 200 250 300 350 50 45 LOAD REGULATION V (mV) 40 35 30 25 20 15 10 5 0 1500 LOAD REGULATION V (mV) 1200 900 600 +5V LOAD = 3A 300 0 0 10 20 30 40 50 60 70 80 0 5 10 15 20 25 30 LOAD CURRENT (mA) SUPPLY VOLTAGE (V) 400 LOAD CURRENT (A) _______________________________________________________________________________________ 7 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 Typical Operating Characteristics (continued) (Circuit of Figure 1, SKIP = GND, TA = +25C, unless otherwise noted.) DROPOUT VOLTAGE vs. LOAD CURRENT (3.3V/3A CIRCUIT) OUTPUT SET FOR 5V (FB = VL) VOUT > 4.85V DROPOUT VOLTAGE (mV) 400 MAX1652 toc09 500 300 f = 300kHz 200 100 f = 150kHz 0 0.01 0.1 1 10 LOAD CURRENT (A) PULSE-WIDTH-MODULATION MODE WAVEFORMS MAX1652-13 IDLE-MODE WAVEFORMS MAX1652-14 OUTPUT VOLTAGE 10mV/div, AC OUTPUT VOLTAGE 50mV/div, AC LX VOLTAGE 5V/div LX VOLTAGE 5V/div TIME (1s) VIN = 6V, 3.3V/3A CIRCUIT TIME (2.5s) ILOAD = 300mA, VIN = 10V, 3.3V/3A CIRCUIT DROPOUT WAVEFORMS MAX1652-15 LOAD-TRANSIENT RESPONSE MAX1652-16 OUTPUT VOLTAGE 10mV/div, AC OUTPUT VOLTAGE 100mV/div, AC LX VOLTAGE 5V/div LOAD CURRENT TIME (5s) VIN = 5.1V, NO LOAD, 3.3V/3A CIRCUIT, SET TO 5V OUTPUT (FB = VL) TIME (10s) VIN = 15V, 3.3V/3A CIRCUIT 2A/div 8 _______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP Pin Description PIN 1 NAME SS SECFB (MAX1652/ MAX1654) 2 SKIP (MAX1653/ MAX1655) 3 4 5 REF GND SYNC FUNCTION Soft-Start Timing Capacitor Connection. Ramp time to full current limit is approximately 1ms/nF. Secondary Winding Feedback Input. Normally connected to a resistor divider from an auxiliary output. Don't leave SECFB unconnected. * MAX1652: SECFB regulates at VSECFB = 2.50V. Tie to VL if not used. * MAX1654: SECFB regulates at VSECFB = 0V. Tie to a negative voltage through a high-value currentlimiting resistor (IMAX = 100A) if not used. Disables pulse-skipping mode when high. Connect to GND for normal use. Don't leave SKIP unconnected. With SKIP grounded, the device will automatically change from pulse-skipping operation to full PWM operation when the load current exceeds approximately 30% of maximum (Table 3). Reference Voltage Output. Bypass to GND with 0.33F minimum. Low-Noise Analog Ground and Feedback Reference Point Oscillator Synchronization and Frequency Select. Tie to GND or VL for 150kHz operation; tie to REF for 300kHz operation. A high-to-low transition begins a new cycle. Drive SYNC with 0 to 5V logic levels (see the Electrical Characteristics table for VIH and VIL specifications). SYNC capture range is 190kHz to 340kHz. Shutdown Control Input, active low. Logic threshold is set at approximately 1V (VTH of an internal N-channel MOSFET). Tie SHDN to V+ for automatic start-up. Feedback Input. Regulates at the feedback voltage in adjustable mode. FB is a Dual ModeTM input that also selects the fixed output voltage settings as follows: * Connect to GND for 3.3V operation. * Connect to VL for 5V operation. * Connect FB to a resistor divider for adjustable mode. FB can be driven with +5V CMOS logic in order to change the output voltage under system control. Current-Sense Input, high side. Current-limit level is 100mV referred to CSL. Current-Sense Input, low side. Also serves as the feedback input in fixed-output modes. Battery Voltage Input (4.5V to 30V). Bypass V+ to PGND close to the IC with a 0.1F capacitor. Connects to a linear regulator that powers VL. 5V Internal Linear-Regulator Output. VL is also the supply voltage rail for the chip. VL is switched to the output voltage via CSL (VCSL > 4.5V) for automatic bootstrapping. Bypass to GND with 4.7F. VL can supply up to 5mA for external loads. Power Ground Low-Side Gate-Drive Output. Normally drives the synchronous-rectifier MOSFET. Swings from 0V to VL. Boost Capacitor Connection for High-Side Gate Drive (0.1F) Switching Node (inductor) Connection. Can swing 2V below ground without hazard. High-Side Gate-Drive Output. Normally drives the main buck switch. DH is a floating driver output that swings from LX to BST, riding on the LX switching-node voltage. MAX1652-MAX1655 6 SHDN 7 FB 8 9 10 CSH CSL V+ 11 12 13 14 15 16 VL PGND DL BST LX DH Dual Mode is a trademark of Maxim Integrated Products. _______________________________________________________________________________________ 9 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 Standard Application Circuits It's easy to adapt the basic MAX1653 single-output 3.3V buck converter (Figure 1) to meet a wide range of applications with inputs up to 30V (limited by choice of external MOSFET). Simply substitute the appropriate components from Table 1 (candidate suppliers are provided in Table 2). These circuits represent a good set of trade-offs among cost, size, and efficiency while staying within the worst-case specification limits for stress-related parameters such as capacitor ripple current. Don't change the frequency of these circuits without first recalculating component values (particularly inductance value at maximum battery voltage). For a discussion of dual-output circuits using the MAX1652 and MAX1654, see Figure 9 and the Secondary Feedback-Regulation Loop section. Detailed Description The MAX1652 family are BiCMOS, switch-mode powersupply controllers designed primarily for buck-topology regulators in battery-powered applications where high efficiency and low quiescent supply current are critical. The parts also work well in other topologies such as boost, inverting, and Cuk due to the flexibility of their floating high-speed gate driver. Light-load efficiency is enhanced by automatic idle-mode operation--a variable-frequency pulse-skipping mode that reduces losses due to MOSFET gate charge. The step-down power-switching circuit consists of two N-channel MOSFETs, a rectifier, and an LC output filter. The output voltage is the average of the AC voltage at the switching node, which is adjusted and regulated by changing the duty cycle of the MOSFET switches. The gate-drive signal to the N-channel high-side MOSFET must exceed the battery voltage and is provided by a flying capacitor boost circuit that uses a 100nF capacitor connected to BST. INPUT C1 C7 0.1F 10 V+ ON/OFF CONTROL 6 SHDN 11 VL DH BST 2 16 14 15 C3 0.1F L1 R1 C2 Q2 D1 GND OUT +3.3V OUTPUT D2 CMPSH-3 Q1 C4 4.7F +5V AT 5mA LOW-NOISE CONTROL SKIP MAX1653 LX DL PGND 1 C6 0.01F (OPTIONAL) FB 7 NOTE: KEEP CURRENT-SENSE LINES SHORT AND CLOSE TOGETHER. SEE FIGURE 8. SYNC 5 SS CSH CSL GND REF 13 12 8 9 4 3 C5 0.33F J1 150kHz/300kHz JUMPER REF OUTPUT +2.5V AT 100A Figure 1. Standard 3.3V Application Circuit (see Table 1 for Component Values) 10 ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP Table 1. Component Selection for Standard Applications COMPONENT Input Range Frequency 3.3V at 1A 4.75V to 28V 300kHz 3.3V at 2A 4.75V to 28V 300kHz International Rectifier 1/2 IRF7303 or Fairchild Semiconductor 1/2 NDS8936 International Rectifier 1/2 IRF7303 or Fairchild Semiconductor 1/2 NDS8936 22F, 35V AVX TPSE226M035R0300 220F, 10V AVX TPSE227M010R0100 or Sprague 594D227X001002T 1N5819 or Motorola MBRS130LT3 MAX1652-MAX1655 5V/3.3V at 3A 4.75V to 28V 300kHz International Rectifier IRF7403 or Fairchild Semiconductor NDS 8410A International Rectifier IRF7403 or Fairchild Semiconductor NDS 8410A (2) 22F, 35V AVX TPSE226M035R0300 470F, 6V (for 3.3V) Kemet T510X477M006AS or (2) 220F, 10V (for 5V) AVX TPSE227M010R011 1N5819 or Motorola MBRS130LT3 3.3V at 5A 4.75V to 28V 300kHz Fairchild Semiconductor FDS6680 1.8V at 2.5A 4.75V to 22V 150kHz Q1 High-Side International Rectifier MOSFET 1/2 IRF7101 International Rectifier 1/2 IRF7303 or Fairchild Semiconductor 1/2 NDS8936 International Rectifier 1/2 IRF7303 or Fairchild Semiconductor 1/2 NDS8936 10F, 25V ceramic Taiyo Yuden TMK325F106Z 470F, 4V Sprague 594D477X0004R2T or 470F, 6V Kemet T510X477M006AS 1N5817 or Motorola MBRS130LT3 30m Dale WSL-2010-R030F or IRC LR2010-01-R030 Q2 Low-Side MOSFET International Rectifier 1/2 IRF7101 Fairchild Semiconductor FDS6680 (3) 22F, 35V AVX TPSE226M035R0300 (3) 330F, 10V Sprague 594D337X0010R2T or (2) 470F, 6V Kemet T510X477M006AS 1N5821 or Motorola MBRS340T3 C1 Input Capacitor 10F, 35V AVX TPSD106M035R0300 C2 Output Capacitor 100F, 6.3V AVX TPSC107M006R D1 Rectifier R1 Sense Resistor 1N5819 or Motorola MBR0520L 70m 33m 25m 12m Dale WSL-1206-R070F Dale WSL-2010-R033F Dale WSL-2010-R025F Dale WSL-2512-R012F or IRC LR2010-01-R070 or IRC LR2010-01-R033 or IRC LR2010-01-R025 33H Sumida CDR74B-330 15H 10H Sumida CDR105B-150 Sumida CDRH125-100 L1 Inductor 4.7H 15H Sumida CDRH127-4R7 Sumida CDRH125-150 Table 2. Component Suppliers MANUFACTURER AVX Central Semiconductor Coilcraft Coiltronics Dale Fairchild International Rectifier IRC Kemet Matsuo Motorola USA PHONE 803-946-0690 516-435-1110 847-639-6400 561-241-7876 605-668-4131 408-822-2181 310-322-3331 512-992-7900 408-986-0424 714-969-2491 602-303-5454 FACTORY FAX [Country Code] [1] 803-626-3123 [1] 516-435-1824 [1] 847-639-1469 [1] 561-241-9339 [1] 605-665-1627 [1] 408-721-1635 [1] 310-322-3332 [1] 512-992-3377 [1] 408-986-1442 [1] 714-960-6492 [1] 602-994-6430 MANUFACTURER Murata NIEC Sanyo Siliconix Sprague Sumida Taiyo Yuden TDK Transpower Technologies * Distributor ______________________________________________________________________________________ 11 USA PHONE 814-237-1431 800-831-9172 805-867-2555* 619-661-6835 408-988-8000 800-554-5565 603-224-1961 847-956-0666 408-573-4150 847-390-4461 702-831-0140 FACTORY FAX [Country Code] [1] 814-238-0490 [81] 3-3494-7414 [81] 7-2070-1174 [1] 408-970-3950 [1] 603-224-1430 [81] 3-3607-5144 [1] 408-573-4159 [1] 847-390-4405 [1] 702-831-3521 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 The MAX1652-MAX1655 contain nine major circuit blocks, which are shown in Figure 2: PWM Controller Blocks: * Multi-Input PWM Comparator * Current-Sense Circuit * PWM Logic Block * Dual-Mode Internal Feedback Mux * Gate-Driver Outputs * Secondary Feedback Comparator Bias Generator Blocks: * +5V Linear Regulator * Automatic Bootstrap Switchover Circuit * +2.50V Reference These internal IC blocks aren't powered directly from the battery. Instead, a +5V linear regulator steps down the battery voltage to supply both the IC internal rail (VL pin) as well as the gate drivers. The synchronousswitch gate driver is directly powered from +5V VL, while the high-side-switch gate driver is indirectly powered from VL via an external diode-capacitor boost circuit. An automatic bootstrap circuit turns off the +5V linear regulator and powers the IC from its output voltage if the output is above 4.5V. charge losses. The oscillator is effectively gated off at light loads because the Idle Mode comparator immediately resets the high-side latch at the beginning of each cycle, unless the feedback signal falls below the reference voltage level. When in PWM mode, the controller operates as a fixedfrequency current-mode controller where the duty ratio is set by the input/output voltage ratio. The currentmode feedback system regulates the peak inductor current as a function of the output voltage error signal. Since the average inductor current is nearly the same as the peak current, the circuit acts as a switch-mode transconductance amplifier and pushes the second output LC filter pole, normally found in a duty-factorcontrolled (voltage-mode) PWM, to a higher frequency. To preserve inner-loop stability and eliminate regenerative inductor current "staircasing," a slope-compensation ramp is summed into the main PWM comparator to reduce the apparent duty factor to less than 50%. The relative gains of the voltage- and current-sense inputs are weighted by the values of current sources that bias three differential input stages in the main PWM comparator (Figure 4). The relative gain of the voltage comparator to the current comparator is internally fixed at K = 2:1. The resulting loop gain (which is relatively low) determines the 2% typical load regulation error. The low loop-gain value helps reduce output filter capacitor size and cost by shifting the unity-gain crossover to a lower frequency. The output filter capacitor C2 sets a dominant pole in the feedback loop. This pole must roll off the loop gain to unity before the zero introduced by the output capacitor's parasitic resistance (ESR) is encountered (see Design Procedure section). A 12kHz pole-zero cancellation filter provides additional rolloff above the unity-gain crossover. This internal 12kHz lowpass compensation filter cancels the zero due to the filter capacitor's ESR. The 12kHz filter is included in the loop in both fixed- and adjustable-output modes. PWM Controller Block The heart of the current-mode PWM controller is a multi-input open-loop comparator that sums three signals: output voltage error signal with respect to the reference voltage, current-sense signal, and slope compensation ramp (Figure 3). The PWM controller is a direct summing type, lacking a traditional error amplifier and the phase shift associated with it. This directsumming configuration approaches the ideal of cycle-by-cycle control over the output voltage. Under heavy loads, the controller operates in full PWM mode. Each pulse from the oscillator sets the main PWM latch that turns on the high-side switch for a period determined by the duty factor (approximately VOUT/VIN). As the high-side switch turns off, the synchronous rectifier latch is set. 60ns later the low-side switch turns on, and stays on until the beginning of the next clock cycle (in continuous mode) or until the inductor current crosses zero (in discontinuous mode). Under fault conditions where the inductor current exceeds the 100mV current-limit threshold, the highside latch resets and the high-side switch turns off. If the load is light in Idle Mode (SKIP = low), the inductor current does not exceed the 25mV threshold set by the Idle Mode comparator. When this occurs, the controller skips most of the oscillator pulses in order to reduce the switching frequency and cut back gate12 Synchronous-Rectifier Driver (DL Pin) Synchronous rectification reduces conduction losses in the rectifier by shunting the normal Schottky diode with a low-resistance MOSFET switch. The synchronous rectifier also ensures proper start-up of the boost-gate driver circuit. If you must omit the synchronous power MOSFET for cost or other reasons, replace it with a small-signal MOSFET such as a 2N7002. If the circuit is operating in continuous-conduction mode, the DL drive waveform is simply the complement of the DH high-side drive waveform (with controlled dead time to prevent cross-conduction or "shoot-through"). ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 BATTERY VOLTAGE TO CSL V+ 4.5V +5V LINEAR REGULATOR SHDN OUT VL +5V AT 5mA AUXILIARY OUTPUT BST SECFB PWM LOGIC DH LX MAIN OUTPUT DL +2.50V REF PWM COMPARATOR REF CSL GND LPF 12kHz PGND +2.50V AT 100A CSH 3.3V FB ON/OFF 5V FB SHDN SS ADJ FB FB MAX1652 MAX1653 MAX1654 MAX1655 SYNC 4V 1V Figure 2. MAX1652-MAX1655 Functional Diagram ______________________________________________________________________________________ 13 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 CSH 2.5V (1V, MAX1655) CSL FROM FEEDBACK DIVIDER MAIN PWM COMPARATOR R Q S LEVEL SHIFT BST DH LX SLOPE COMP IDLE MODE COMPARATOR SKIP (MAX1653/ MAX1655 ONLY) 25mV OSC VL 4A CURRENT LIMIT SHOOTTHROUGH CONTROL SS 24R 2.5V SHDN N 1R SYNCHRONOUSRECTIFIER CONTROL R -100mV S VL Q LEVEL SHIFT DL PGND REF (MAX1652) GND (MAX1654) SECFB COMPARATOR 1s SINGLE-SHOT (NOTE 1) MAX1652, MAX1654 ONLY NOTE 1: COMPARATOR INPUT POLARITIES ARE REVERSED FOR THE MAX1654. Figure 3. PWM Controller Detailed Block Diagram 14 ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 VL R1 R2 TO PWM LOGIC UNCOMPENSATED HIGH-SPEED LEVEL TRANSLATOR AND BUFFER OUTPUT DRIVER I1 I2 I3 FB REF CSH CSL SLOPE COMPENSATION Figure 4. Main PWM Comparator Block Diagram In discontinuous (light-load) mode, the synchronous switch is turned off as the inductor current falls through zero. The synchronous rectifier works under all operating conditions, including idle mode. The synchronousswitch timing is further controlled by the secondary feedback (SECFB) signal in order to improve multipleoutput cross-regulation (see Secondary FeedbackRegulation Loop section). Internal VL and REF Supplies An internal regulator produces the 5V supply (VL) that powers the PWM controller, logic, reference, and other blocks. This +5V low-dropout linear regulator can supply up to 5mA for external loads, with a reserve of 20mA for gate-drive power. Bypass VL to GND with 4.7F. Important: VL must not be allowed to exceed 5.5V. Measure VL with the main output fully loaded. If VL is being pumped up above 5.5V, the probable cause is either excessive boost-diode capacitance or excessive ripple at V+. Use only small-signal diodes for D2 (10mA to 100mA Schottky or 1N4148 are preferred) and bypass V+ to PGND with 0.1F directly at the package pins. The 2.5V reference (REF) is accurate to 1.6% over temperature, making REF useful as a precision system reference. Bypass REF to GND with 0.33F minimum. REF can supply up to 1mA for external loads. However, if tight-accuracy specs for either V OUT or REF are essential, avoid loading REF with more than 100A. Loading REF reduces the main output voltage slightly, according to the reference-voltage load regulation error. In MAX1654 applications, ensure that the SECFB divider doesn't load REF heavily. When the main output voltage is above 4.5V, an internal P-channel MOSFET switch connects CSL to VL while simultaneously shutting down the VL linear regulator. This action bootstraps the IC, powering the internal circuitry from the output voltage, rather than through a linear regulator from the battery. Bootstrapping reduces power dissipation caused by gate-charge and quiescent losses by providing that power from a 90%-efficient switch-mode source, rather than from a less efficient linear regulator. It's often possible to achieve a bootstrap-like effect, even for circuits that are set to VOUT < 4.5V, by powering VL from an external-system +5V supply. To achieve this pseudo-bootstrap, add a Schottky diode between the external +5V source and VL, with the cathode to the VL side. This circuit provides a 1% to 2% efficiency boost and also extends the minimum battery input to less than 4V. The external source must be in the range of 4.8V to 5.5V. Boost High-Side Gate-Driver Supply (BST Pin) Gate-drive voltage for the high-side N-channel switch is generated by a flying-capacitor boost circuit as shown in Figure 5. The capacitor is alternately charged from the VL supply and placed in parallel with the high-side MOSFET's gate-source terminals. On start-up, the synchronous rectifier (low-side MOSFET) forces LX to 0V and charges the BST capacitor to 5V. On the second half-cycle, the PWM turns on the high-side MOSFET by closing an internal switch between BST and DH. This provides the necessary enhancement voltage to turn on the high-side switch, 15 ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 BATTERY +5V VL SUPPLY INPUT Oscillator Frequency and Synchronization (SYNC Pin) The SYNC input controls the oscillator frequency. Connecting SYNC to GND or to VL selects 150kHz operation; connecting SYNC to REF selects 300kHz. SYNC can also be used to synchronize with an external 5V CMOS clock generator. SYNC has a guaranteed 190kHz to 340kHz capture range. 300kHz operation optimizes the application circuit for component size and cost. 150kHz operation provides increased efficiency and improved low-duty factor operation (see Dropout Operation section). VL MAX1652 MAX1653 MAX1654 MAX1655 LEVEL TRANSLATOR VL BST DH LX VL PWM Dropout Operation DL Figure 5. Boost Supply for Gate Drivers Dropout (low input-output differential operation) is enhanced by stretching the clock pulse width to increase the maximum duty factor. The algorithm follows: if the output voltage (VOUT) drops out of regulation without the current limit having been reached, the controller skips an off-time period (extending the on-time). At the end of the cycle, if the output is still out of regulation, another off-time period is skipped. This action can continue until three offtime periods are skipped, effectively dividing the clock frequency by as much as four. The typical PWM minimum off-time is 300ns, regardless of the operating frequency. Lowering the operating frequency raises the maximum duty factor above 98%. an action that "boosts" the 5V gate-drive signal above the battery voltage. Ringing seen at the high-side MOSFET gate (DH) in discontinuous-conduction mode (light loads) is a natural operating condition caused by the residual energy in the tank circuit formed by the inductor and stray capacitance at the switching node LX. The gate-driver negative rail is referred to LX, so any ringing there is directly coupled to the gate-drive output. Low-Noise Mode (SKIP Pin) The low-noise mode (SKIP = high) is useful for minimizing RF and audio interference in noise-sensitive applications such as audio-equipped systems, cellular phones, RF communicating computers, and electromagnetic pen-entry systems. See the summary of operating modes in Table 3. SKIP can be driven from an external logic signal. The MAX1653 and MAX1655 can reduce interference due to switching noise by ensuring a constant switching frequency regardless of load and line conditions, thus concentrating the emissions at a known frequency outside the system audio or IF bands. Choose an oscillator frequency where harmonics of the switching frequency don't overlap a sensitive frequency band. If necessary, synchronize the oscillator to a tight-tolerance external clock generator. The low-noise mode (SKIP = high) forces two changes upon the PWM controller. First, it ensures fixed-frequency operation by disabling the minimum-current comparator and ensuring that the PWM latch is set at the beginning of each cycle, even if the output is in regulation. Second, it ensures continuous inductor current Current-Limiting and Current-Sense Inputs (CSH and CSL) The current-limit circuit resets the main PWM latch and turns off the high-side MOSFET switch whenever the voltage difference between CSH and CSL exceeds 100mV. This limiting is effective for both current flow directions, putting the threshold limit at 100mV. The tolerance on the positive current limit is 20%, so the external low-value sense resistor must be sized for 80mV/R1 to guarantee enough load capability, while components must be designed to withstand continuous current stresses of 120mV/R1. For breadboarding purposes or very-high-current applications, it may be useful to wire the current-sense inputs with a twisted pair rather than PC traces. 16 ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP Table 3. Operating-Mode Truth Table SHDN Low SKIP X LOAD CURRENT X MODE NAME Shutdown DESCRIPTION All circuit blocks turned off; supply current = 3A typ Pulse-skipping; supply current = 300A typ at VIN = 10V; discontinuous inductor current Pulse-skipping; continuous inductor current Constant-frequency PWM; continuous inductor current High Low Low, <10% Idle High Low Medium, <30% High, >30% Idle High Low PWM put. Adjusting the main output voltage with external resistors is easy for any of the devices in this family, via the circuit of Figure 6. The feedback voltage is nominally 2.5 for all family members except the MAX1655, which has a nominal FB voltage of 1V. The output voltage (given by the formula in Figure 6) should be set approximately 2% high in order to make up for the MAX1652's load-regulation error. For example, if designing for a 3.0V output, use a resistor ratio that results in a nominal output voltage of 3.06V. This slight offsetting gives the best possible accuracy. Recommended normal values for R5 range from 5k to 100k. Remote sensing of the output voltage, while not possible in fixed-output mode due to the combined nature of the voltage- and current-sense input (CSL), is easy to achieve in adjustable mode by using the top of the external resistor divider as the remote sense point. MAX1652-MAX1655 High High X Constant-frequency PWM regardless of Low Noise* load; continuous (PWM) inductor current even at no load Duty-Factor Limitations for Low VOUT/VIN Ratios The MAX1652/MAX1653/MAX1654's output voltage is adjustable down to 2.5V and the MAX1655's output is adjustable as low as 1V. However, the minimum duty factor may limit the choice of operating frequency, high input voltage, and low output voltage. * MAX1652/MAX1654 have no SKIP pin and therefore can't go into low-noise mode. X = Don't care flow, and thereby suppresses discontinuous-mode inductor ringing by changing the reverse current-limit detection threshold from 0 to -100mV, allowing the inductor current to reverse at very light loads. In most applications, SKIP should be tied to GND in order to minimize quiescent supply current. Supply current with SKIP high is typically 10mA to 20mA, depending on external MOSFET gate capacitance and switching losses. Forced continuous conduction via SKIP can improve cross regulation of transformer-coupled multiple-output supplies. This second function of the SKIP pin produces a result that is similar to the method of adding secondary regulation via the SECFB feedback pin, but with much higher quiescent supply current. Still, improving cross regulation by enabling SKIP instead of building in SECFB feedback can be useful in noise-sensitive applications, since SECFB and SKIP are mutually exclusive pins/functions in the MAX1652 family. DH V+ REMOTE SENSE LINES MAIN OUTPUT MAX1652 MAX1653 DL MAX1654 MAX1655 CSH CSL FB GND R5 R4 VOUT = VREF R4 (1 + ---) R5 Adjustable-Output Feedback (Dual-Mode FB Pin) The MAX1652-MAX1655 family has both fixed and adjustable output voltage modes. For fixed mode, connect FB to GND for a 3.3V output and to VL for a 5V out- WHERE VREF (NOMINAL) = 2.5V (MAX1652-MAX1654) = 1.0V (MAX1655) Figure 6. Adjusting the Main Output Voltage ______________________________________________________________________________________ 17 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 With high input voltages, the required duty factor is approximately (VOUT + VQ2)/ VIN, where VQ2 is the voltage drop across the synchronous rectifier. The MAX1652's minimum duty factor is determined by delays through the feedback network, error comparator, internal logic gate drivers, and the external MOSFETs, which typically total 400ns. This delay is about 12% of the switching period at 300kHz and 6% at 150kHz, limiting the typical minimum duty factor to these values. Even if the circuit can not attain the required duty factor dictated by the input and output voltages, the output voltage will remain in regulation. However, there may be intermittent or continuous half-frequency operation. This can cause a factor-of-two increase in output voltage ripple and current ripple, which will increase noise and reduce efficiency. Choose 150kHz operation for highinput-voltage/low-output-voltage circuits. on-time beyond the point where the inductor current crosses zero (in discontinuous mode). This causes the inductor (primary) current to reverse, which in turn pulls current out of the output filter capacitor and causes the flyback transformer to operate in the forward mode. The low impedance presented by the transformer secondary in the forward mode dumps current into the secondary output, charging up the secondary capacitor and bringing SECFB back into regulation. The SECFB feedback loop does not improve secondary output accuracy in normal flyback mode, where the main (primary) output is heavily loaded. In this mode, secondary output accuracy is determined (as usual) by the secondary rectifier drop, turns ratio, and accuracy of the main output voltage. Hence, a linear post-regulator may still be needed in order to meet tight output accuracy specifications. The secondary output voltage-regulation point is determined by an external resistor-divider at SECFB. For negative output voltages, the SECFB comparator is referenced to GND (MAX1654); for positive output voltages, SECFB regulates at the 2.50V reference (MAX1652). As a result, output resistor-divider connections and design equations for the two device types differ slightly (Figure 7). Ordinarily, the secondary regulation point is set 5% to 10% below the voltage normally produced by the flyback effect. For example, if the Secondary Feedback-Regulation Loop (SECFB Pin) A flyback winding control loop regulates a secondary winding output (MAX1652/MAX1654 only), improving cross-regulation when the primary is lightly loaded or when there is a low input-output differential voltage. If SECFB crosses its regulation threshold, a 1s oneshot is triggered that extends the low-side switch's 0.33F R3 SECFB 1-SHOT TRIG 2.5V REF V+ 1-SHOT TRIG POSITIVE SECONDARY OUTPUT REF SECFB R3 R2 R2 V+ NEGATIVE SECONDARY OUTPUT DH DH MAX1652 DL MAIN OUTPUT MAX1654 DL MAIN OUTPUT +VTRIP = VREF R2 (1 + ---) R3 WHERE VREF (NOMINAL) = 2.5V -VTRIP = -VREF R2 (---) R3 R3 = 100k (RECOMMENDED) Figure 7. Secondary-Output Feedback Dividers 18 ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP output voltage as determined by the turns ratio is +15V, the feedback resistor ratio should be set to produce about +13.5V; otherwise, the SECFB one-shot might be triggered unintentionally, causing an unnecessary increase in supply current and output noise. In negativeoutput (MAX1654) applications, the resistor-divider acts as a load on the internal reference, which in turn can cause errors at the main output. Avoid overloading REF (see the Reference Load-Regulation Error vs. Load Current graph in the Typical Operating Characteristics). 100k is a good value for R3 in MAX1654 circuits. Output current on secondary winding applications is limited at low input voltages. See the MAX1652 Maximum Secondary Output Current vs. Supply Voltage graph in the Typical Operating Characteristics for data from the application circuit of Figure 8. input surge currents, and perhaps for power-supply sequencing. In shutdown mode, the soft-start circuit holds the SS capacitor discharged to ground. When SHDN goes high, a 4A current source charges the SS capacitor up to 3.2V. The resulting linear ramp waveform causes the internal current-limit level to increase proportionally from 0 to 100mV. The main output capacitor thus charges up relatively slowly, depending on the SS capacitor value. The exact time of the output rise depends on output capacitance and load current and is typically 1ms per nanofarad of soft-start capacitance. With no SS capacitor connected, maximum current limit is reached within 10s. MAX1652-MAX1655 Shutdown Shutdown mode (SHDN = 0V) reduces the V+ supply current to typically 3A. In this mode, the reference and VL are inactive. SHDN is a logic-level input, but it can be safely driven to the full V+ range. Connect SHDN to V+ for automatic start-up. Do not allow slow transitions (slower than 0.02V/s) on SHDN. Soft-Start Circuit (SS) Soft-start allows a gradual increase of the internal current-limit level at start-up for the purpose of reducing 22F, 35V VIN (6.5V TO 18V) 22F, 35V C2 4.7F V+ DH SHDN BST 10 16 14 0.1F 15 D1 CMPSH -3A Si9410 D2 EC11FS1 210k, 1% C2 4.7F C3 15F 2.5V 0.01F 49.9k, 1% +15V AT 250mA 2 SECFB 7 FB 11 VL ON/OFF 6 18V 1/4 W +5V AT 3A MAX1652 1 SS LX T1 15H 2.2:1 Si9410 1N5819 20m 220F 10V 220F 10V DL PGND 13 12 0.01F (OPTIONAL) 4 GND CSH CSL SYNC 5 3 0.33F REF 8 9 4700pF* T1 = TRANSPOWER TTI5870 * = OPTIONAL, MAY NOT BE NEEDED 22* Figure 8. 5V/15V Dual-Output Application Circuit (MAX1652) ______________________________________________________________________________________ 19 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 __________________Design Procedure The predesigned standard application circuits (Figure 1 and Table 1) contain ready-to-use solutions for common applications. Use the following design procedure to optimize the basic schematic for different voltage or current requirements. Before beginning a design, firmly establish the following: VIN(MAX), the maximum input (battery) voltage. This value should include the worst-case conditions, such as no-load operation when a battery charger or AC adapter is connected but no battery is installed. VIN(MAX) must not exceed 30V. This 30V upper limit is determined by the breakdown voltage of the BST floating gate driver to GND (36V absolute maximum). VIN(MIN), the minimum input (battery) voltage. This should be at full-load under the lowest battery conditions. If VIN(MIN) is less than 4.5V, a special circuit must be used to externally hold up VL above 4.8V. If the minimum input-output difference is less than 1V, the filter capacitance required to maintain good AC load regulation increases. AC current to DC load current. A higher value of LIR allows smaller inductance, but results in higher losses and ripple. A good compromise between size and losses is found at a 30% ripple current to load current ratio (LIR = 0.3), which corresponds to a peak inductor current 1.15 times higher than the DC load current. VOUT (VIN(MAX) - VOUT) L = ---------------------- VIN(MAX) x f x IOUT x LIR f = switching frequency, normally 150kHz or 300kHz IOUT = maximum DC load current LIR = ratio of AC to DC inductor current, typically 0.3 The peak inductor current at full load is 1.15 x IOUT if the above equation is used; otherwise, the peak current can be calculated by: IPEAK = ILOAD + VOUT (VIN(MAX) - VOUT ) 2 x f x L x VIN(MAX) where: Inductor Value The exact inductor value isn't critical and can be adjusted freely in order to make trade-offs among size, cost, and efficiency. Although lower inductor values will minimize size and cost, they will also reduce efficiency due to higher peak currents. To permit use of the physically smallest inductor, lower the inductance until the circuit is operating at the border between continuous and discontinuous modes. Reducing the inductor value even further, below this crossover point, results in discontinuous-conduction operation even at full load. This helps reduce output filter capacitance requirements but causes the core energy storage requirements to increase again. On the other hand, higher inductor values will increase efficiency, but at some point resistive losses due to extra turns of wire will exceed the benefit gained from lower AC current levels. Also, high inductor values affect load-transient response; see the VSAG equation in the Low-Voltage Operation section. The following equations are given for continuous-conduction operation since the MAX1652 family is mainly intended for high-efficiency, battery-powered applications. See Appendix A in Maxim's Battery Management and DC-DC Converter Circuit Collection for crossover point and discontinuous-mode equations. Discontinuous conduction doesn't affect normal Idle Mode operation. Three key inductor parameters must be specified: inductance value (L), peak current (IPEAK), and DC resistance (RDC). The following equation includes a constant LIR, which is the ratio of inductor peak-to-peak 20 The inductor's DC resistance is a key parameter for efficiency performance and must be ruthlessly minimized, preferably to less than 25m at IOUT = 3A. If a standard off-the-shelf inductor is not available, choose a core with an LI2 rating greater than L x IPEAK2 and wind it with the largest diameter wire that fits the winding area. For 300kHz applications, ferrite core material is strongly preferred; for 150kHz applications, Kool-mu (aluminum alloy) and even powdered iron can be acceptable. If light-load efficiency is unimportant (in desktop 5V-to-3V applications, for example) then lowpermeability iron-powder cores may be acceptable, even at 300kHz. For high-current applications, shielded core geometries (such as toroidal or pot core) help keep noise, EMI, and switching-waveform jitter low. Current-Sense Resistor Value The current-sense resistor value is calculated according to the worst-case, low-current-limit threshold voltage (from the Electrical Characteristics table) and the peak inductor current. The continuous-mode peak inductorcurrent calculations that follow are also useful for sizing the switches and specifying the inductor-current saturation ratings. In order to simplify the calculation, ILOAD may be used in place of IPEAK if the inductor value has been set for LIR = 0.3 or less (high inductor values) and 300kHz operation is selected. Low-inductance resistors, such as surface-mount metal-film resistors, are preferred. 80mV RSENSE = -------- IPEAK ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP Input Capacitor Value Place a small ceramic capacitor (0.1F) between V+ and GND, close to the device. Also, connect a low-ESR bulk capacitor directly to the drain of the high-side MOSFET. Select the bulk input filter capacitor according to input ripple-current requirements and voltage rating, rather than capacitor value. Electrolytic capacitors that have low enough effective series resistance (ESR) to meet the ripple-current requirement invariably have more than adequate capacitance values. Ceramic capacitors or low-ESR aluminum-electrolytic capacitors such as Sanyo OS-CON or Nichicon PL are preferred. Tantalum types are also acceptable but may be less tolerant of high input surge currents. RMS input ripple current is determined by the input voltage and load current, with the worst possible case occurring at VIN = 2 x VOUT: IRMS = ILOAD x VOUT (VIN - VOUT) VIN first symptom is a bit of timing jitter, which shows up as blurred edges in the switching waveforms where the scope won't quite sync up. Technically speaking, this (usually) harmless jitter is unstable operation, since the switching frequency is now nonconstant. As the capacitor quality is reduced, the jitter becomes more pronounced and the load-transient output voltage waveform starts looking ragged at the edges. Eventually, the load-transient waveform has enough ringing on it that the peak noise levels exceed the allowable output voltage tolerance. Note that even with zero phase margin and gross instability present, the output voltage noise never gets much worse than IPEAK x RESR (under constant loads, at least). Note: Designers of RF communicators or other noisesensitive analog equipment should be conservative and stick to the ESR guidelines. Designers of notebook computers and similar commercial-temperature-range digital systems can multiply the RESR value by a factor of 1.5 without hurting stability or transient response. The output voltage ripple is usually dominated by the ESR of the filter capacitor and can be approximated as IRIPPLE x RESR. There is also a capacitive term, so the full equation for ripple in the continuous mode is VNOISE(p-p) = IRIPPLE x [RESR + 1 / (8 x f x COUT)]. In Idle Mode, the inductor current becomes discontinuous with high peaks and widely spaced pulses, so the noise can actually be higher at light load compared to full load. In Idle Mode, the output ripple can be calculated as: 0.025 x RESR VNOISE(p-p) = ------------ + RSENSE (0.025)2 x L x [1 / VOUT + 1 / (VIN - VOUT)] -------------------------------------- (RSENSE)2 x COUT MAX1652-MAX1655 IRMS = ILOAD / 2 when VIN is 2 x VOUT Output Filter Capacitor Value The output filter capacitor values are determined by the ESR, capacitance, and voltage rating requirements. Electrolytic and tantalum capacitors are generally chosen by voltage rating and ESR specifications, as they will generally have more output capacitance than is required for AC stability. Use only specialized low-ESR capacitors intended for switching-regulator applications, such as AVX TPS, Sprague 595D, Sanyo OS-CON, or Nichicon PL series. To ensure stability, the capacitor must meet both minimum capacitance and maximum ESR values as given in the following equations: VREF (1 + VOUT / VIN(MIN)) COUT > ------------------------- VOUT x RSENSE x f RSENSE x VOUT RESR < ---------------- VREF (can be multiplied by 1.5, see note below) These equations are "worst-case" with 45 degrees of phase margin to ensure jitter-free fixed-frequency operation and provide a nicely damped output response for zero to full-load step changes. Some cost-conscious designers may wish to bend these rules by using less expensive (lower quality) capacitors, particularly if the load lacks large step changes. This practice is tolerable if some bench testing over temperature is done to verify acceptable noise and transient response. There is no well-defined boundary between stable and unstable operation. As phase margin is reduced, the Transformer Design (MAX1652/MAX1654 Only) Buck-plus-flyback applications, sometimes called "coupled-inductor" topologies, use a transformer to generate multiple output voltages. The basic electrical design is a simple task of calculating turns ratios and adding the power delivered to the secondary in order to calculate the current-sense resistor and primary inductance. However, extremes of low input-output differentials, widely different output loading levels, and high turns ratios can complicate the design due to parasitic transformer parameters such as interwinding capacitance, secondary resistance, and leakage inductance. For examples of what is possible with real-world transformers, see the graphs of Maximum Secondary Current vs. Input Voltage in the Typical Operating Characteristics. 21 ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 Power from the main and secondary outputs is lumped together to obtain an equivalent current referred to the main output voltage (see Inductor Value section for definitions of parameters). Set the value of the currentsense resistor at 80mV / ITOTAL. PTOTAL = the sum of the output power from all outputs ITOTAL = PTOTAL / VOUT = the equivalent output current referred to VOUT VOUT (VIN(MAX) - VOUT) L(primary) = -------------------------- VIN(MAX) x f x ITOTAL x LIR VSEC + VFWD Turns Ratio N = ---------------------------- VOUT(MIN) + VRECT + VSENSE where: VSEC is the minimum required rectified secondary-output voltage VFWD is the forward drop across the secondary rectifier VOUT(MIN) is the minimum value of the main output voltage (from the Electrical Characteristics) VRECT is the on-state voltage drop across the synchronous-rectifier MOSFET VSENSE is the voltage drop across the sense resistor In positive-output (MAX1652) applications, the transformer secondary return is often referred to the main output voltage rather than to ground in order to reduce the needed turns ratio. In this case, the main output voltage must first be subtracted from the secondary voltage to obtain VSEC. In high-current applications, MOSFET package power dissipation often becomes a dominant design factor. I2R losses are distributed between Q1 and Q2 according to duty factor (see the equations below). Switching losses affect the upper MOSFET only, since the Schottky rectifier clamps the switching node before the synchronous rectifier turns on. Gate-charge losses are dissipated by the driver and don't heat the MOSFET. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. The worst-case dissipation for the high-side MOSFET occurs at the minimum battery voltage, and the worst-case for the low-side MOSFET occurs at the maximum battery voltage. PD (upper FET) = ILOAD2 x RDS(ON) x DUTY + VIN x ILOAD x f x VIN x CRSS (----------- +20ns) I GATE PD (lower FET) = ILOAD2 x RDS(ON) x (1 - DUTY) DUTY = (VOUT + VQ2) / (VIN - VQ1 + VQ2) where the on-state voltage drop VQ_ = ILOAD x RDS(ON) CRSS = MOSFET reverse transfer capacitance IGATE = DH driver peak output current capability (1A typically) 20ns = DH driver inherent rise/fall time Under output short circuit, the synchronous-rectifier MOSFET suffers extra stress and may need to be oversized if a continuous DC short circuit must be tolerated. During short circuit, Q2's duty factor can increase to greater than 0.9 according to: Q2 DUTY (short circuit) = 1 - [VQ2 / (VIN(MAX) - VQ1 + VQ2)] where the on-state voltage drop VQ = (120mV / RSENSE) x RDS(ON). ______Selecting Other Components MOSFET Switches The two high-current N-channel MOSFETs must be logic-level types with guaranteed on-resistance specifications at VGS = 4.5V. Lower gate threshold specs are better (i.e., 2V max rather than 3V max). Drain-source breakdown voltage ratings must at least equal the maximum input voltage, preferably with a 20% derating factor. The best MOSFETs will have the lowest on-resistance per nanocoulomb of gate charge. Multiplying RDS(ON) x QG provides a meaningful figure by which to compare various MOSFETs. Newer MOSFET process technologies with dense cell structures generally give the best performance. The internal gate drivers can tolerate more than 100nC total gate charge, but 70nC is a more practical upper limit to maintain best switching times. 22 Rectifier Diode D1 Rectifier D1 is a clamp that catches the negative inductor swing during the 60ns dead time between turning off the high-side MOSFET and turning on the low-side. D1 must be a Schottky type in order to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit D1 and let the body diode clamp the negative inductor swing, but efficiency will drop one or two percent as a result. Use an MBR0530 (500mA rated) type for loads up to 1.5A, a 1N5819 type for loads up to 3A, or a 1N5822 type for loads up to 10A. D1's rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP Boost-Supply Diode D2 A 10mA to 100mA Schottky diode or signal diode such as a 1N4148 works well for D2 in most applications. If the input voltage can go below 6V, use a Schottky diode for slightly improved efficiency and dropout characteristics. Don't use large power diodes such as 1N5817 or 1N4001, since high junction capacitance can cause VL to be pumped up to excessive voltages. _____________Low-Voltage Operation Low input voltages and low input-output differential voltages each require some extra care in the design. Low absolute input voltages can cause the VL linear regulator to enter dropout, and eventually shut itself off. Low input voltages relative to the output (low VIN-VOUT differential) can cause bad load regulation in multi-output flyback applications. See Transformer Design section. Finally, low VIN-VOUT differentials can also cause the output voltage to sag when the load current changes abruptly. The amplitude of the sag is a function of inductor value and maximum duty factor (DMAX an Electrical Characteristics parameter, 98% guaranteed over temperature at f = 150kHz) as follows: (ISTEP)2 x L VSAG = ------------------------------ 2 x COUT x (VIN(MIN) x DMAX - VOUT) The cure for low-voltage sag is to increase the value of the output capacitor. For example, at VIN = 5.5V, VOUT = 5V, L = 10H, f = 150kHz, a total capacitance of 660F will prevent excessive sag. Note that only the capacitance requirement is increased and the ESR requirements don't change. Therefore, the added capacitance can be supplied by a low-cost bulk capacitor in parallel with the normal low-ESR capacitor. Table 4 summarizes low-voltage operational issues. MAX1652-MAX1655 Rectifier Diode D3 (Transformer Secondary Diode) The secondary diode in coupled-inductor applications must withstand high flyback voltages greater than 60V, which usually rules out most Schottky rectifiers. Common silicon rectifiers such as the 1N4001 are also prohibited, as they are far too slow. This often makes fast silicon rectifiers such as the MURS120 the only choice. The flyback voltage across the rectifier is related to the VIN-VOUT difference according to the transformer turns ratio: VFLYBACK = VSEC + (VIN - VOUT) x N where: N is the transformer turns ratio SEC/PRI VSEC is the maximum secondary DC output voltage VOUT is the primary (main) output voltage Subtract the main output voltage (VOUT) from VFLYBACK in this equation if the secondary winding is returned to VOUT and not to ground. The diode reverse breakdown rating must also accommodate any ringing due to leakage inductance. D3's current rating should be at least twice the DC load current on the secondary output. Table 4. Low-Voltage Troubleshooting SYMPTOM Sag or droop in VOUT under step load change Dropout voltage is too high (VOUT follows VIN as VIN decreases) Unstable--jitters between two distinct duty factors Secondary output won't support a load CONDITION ROOT CAUSE SOLUTION Increase bulk output capacitance per formula above. Reduce inductor value. Reduce f to 150kHz. Reduce MOSFET on-resistance and coil DCR. Increase the minimum input voltage or ignore. Low VIN-VOUT differential, Limited inductor-current slew <1V rate per cycle. Low VIN-VOUT differential, Maximum duty-cycle limits <0.5V exceeded. Low VIN-VOUT differential, Normal function of internal low<0.5V dropout circuitry. Not enough duty cycle left to Reduce f to 150kHz. Reduce secondary Low VIN-VOUT differential, initiate forward-mode operation. impedances--use Schottky if possible. VIN < 1.3 x VOUT(main) Small AC current in primary can't Stack secondary winding on main output. store energy for flyback operation. Low input voltage, <5V VL linear regulator is going into dropout and isn't providing good gate-drive levels. Use a small 20mA Schottky diode for boost diode D2. Supply VL from an external source. High supply current, poor efficiency Won't start under load or quits before battery is completely dead Low input voltage, <4.5V VL output is so low that it hits the Supply VL from an external source other VL UVLO threshold at 4.2V max. than VBATT, such as the system 5V supply. ______________________________________________________________________________________ 23 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 __________Applications Information Heavy-Load Efficiency Considerations The major efficiency loss mechanisms under loads (in the usual order of importance) are: * P(I2R), I2R losses * P(gate), gate-charge losses * P(diode), diode-conduction losses * P(tran), transition losses * P(cap), capacitor ESR losses * P(IC), losses due to the operating supply current of the IC Inductor-core losses are fairly low at heavy loads because the inductor's AC current component is small. Therefore, they aren't accounted for in this analysis. Ferrite cores are preferred, especially at 300kHz, but powdered cores such as Kool-mu can work well. Efficiency = POUT / PIN x 100% = POUT / (POUT + PTOTAL) x 100% PTOTAL = P(I2R) + P(gate) + P(diode) + P(tran) + P(cap) + P(IC) P(I2R) = (ILOAD)2 x (RDC + RDS(ON) + RSENSE) where RDC is the DC resistance of the coil, RDS(ON) is the MOSFET on-resistance, and RSENSE is the currentsense resistor value. The RDS(ON) term assumes identical MOSFETs for the high- and low-side switches because they time-share the inductor current. If the MOSFETs aren't identical, their losses can be estimated by averaging the losses according to duty factor. P(gate) = gate-driver loss = qG x f x VL where VL is the MAX1652 internal logic supply voltage (5V), and qG is the sum of the gate-charge values for low- and high-side switches. For matched MOSFETs, qG is twice the data sheet value of an individual MOSFET. If VOUT is set to less than 4.5V, replace VL in this equation with VBATT. In this case, efficiency can be improved by connecting VL to an efficient 5V source, such as the system +5V supply. P(diode) = diode conduction losses = ILOAD x VFWD x tD x f where tD is the diode conduction time (120ns typ) and VFWD is the forward voltage of the Schottky. PD(tran) = transition loss = VBATT x CRSS VBATT x ILOAD x f x + 20ns) IGATE the DH gate-driver peak output current (1A typ), and 20ns is the rise/fall time of the DH driver. P(cap) = input capacitor ESR loss = (IRMS)2 x RESR where IRMS is the input ripple current as calculated in the Input Capacitor Value section of the Design Procedure. Light-Load Efficiency Considerations Under light loads, the PWM operates in discontinuous mode, where the inductor current discharges to zero at some point during the switching cycle. This causes the AC component of the inductor current to be high compared to the load current, which increases core losses and I2R losses in the output filter capacitors. Obtain best light-load efficiency by using MOSFETs with moderate gate-charge levels and by using ferrite, MPP, or other low-loss core material. Avoid powdered iron cores; even Kool-mu (aluminum alloy) is not as good as ferrite. __PC Board Layout Considerations Good PC board layout is required to achieve specified noise, efficiency, and stability performance. The PC board layout artist must be provided with explicit instructions, preferably a pencil sketch of the placement of power switching components and high-current routing. See the evaluation kit PC board layouts in the MAX1653, MAX796, and MAX797 EV kit manuals for examples. A ground plane is essential for optimum performance. In most applications, the circuit will be located on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high-current connections, the bottom layer for quiet connections (REF, SS, GND), and the inner layers for an uninterrupted ground plane. Use the following stepby-step guide. 1) Place the high-power components (C1, C2, Q1, Q2, D1, L1, and R1) first, with their grounds adjacent. Priority 1: Minimize current-sense resistor trace lengths (see Figure 9). Priority 2: Minimize ground trace lengths in the high-current paths (discussed below). Priority 3: Minimize other trace lengths in the highcurrent paths. Use >5mm wide traces. C1 to Q1: 10mm max length. D1 anode to Q2: 5mm max length LX node (Q1 source, Q2 drain, D1 cathode, inductor): 15mm max length Ideally, surface-mount power components are butted up to one another with their ground terminals almost touching. These high-current grounds (C1-, C2-, source of Q2, anode of D1, and PGND) are then connected to each other with a wide filled zone (-------------- where CRSS is the reverse transfer capacitance of the high-side MOSFET (a data sheet parameter), IGATE is 24 ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP of top-layer copper, so that they don't go through vias. The resulting top-layer "sub-ground-plane" is connected to the normal inner-layer ground plane at the output ground terminals. This ensures that the analog GND of the IC is sensing at the output terminals of the supply, without interference from IR drops and ground noise. Other high-current paths should also be minimized, but focusing ruthlessly on short ground and current-sense connections eliminates about 90% of all PC board layout difficulties. See the evaluation kit PC board layouts for examples. 2) Place the IC and signal components. Keep the main switching node (LX node) away from sensitive analog components (current-sense traces and REF and SS capacitors). Placing the IC and analog components on the opposite side of the board from the power-switching node is desirable. Important: the IC must be no farther than 10mm from the currentsense resistor. Keep the gate-drive traces (DH, DL, and BST) shorter than 20mm and route them away from CSH, CSL, REF, and SS. 3) Employ a single-point star ground where the input ground trace, power ground (subground plane), and normal ground plane all meet at the output ground terminal of the supply. MAX1652-MAX1655 FAT, HIGH-CURRENT TRACES MAIN CURRENT PATH SENSE RESISTOR MAX1652 MAX1653 MAX1654 MAX1655 Figure 9. Kelvin Connections for the Current-Sense Resistor Pin Configurations TOP VIEW SS 1 (SECFB) SKIP 2 REF 3 GND 4 SYNC 5 SHDN 6 FB 7 CSH 8 16 DH 15 LX 14 BST SS 1 SKIP 2 REF 3 GND 4 SYNC 5 SHDN 6 FB 7 CSH 8 16 DH 15 LX 14 BST MAX1652 MAX1653 MAX1654 MAX1655 13 DL 12 PGND 11 VL 10 V+ 9 CSL MAX1653 MAX1655 13 DL 12 PGND 11 VL 10 V+ 9 CSL QSOP ( ) ARE FOR MAX1652/ MAX1654. Narrow SO ______________________________________________________________________________________ 25 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 ___________________Chip Information TRANSISTOR COUNT: 1990 ________________________________________________________Package Information QSOP.EPS 26 ______________________________________________________________________________________ High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP ___________________________________________Package Information (continued) SOICN.EPS MAX1652-MAX1655 ______________________________________________________________________________________ 27 High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP MAX1652-MAX1655 NOTES 28 ______________________________________________________________________________________ |
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